Photoresponsive and photovoltaic materials and devices constructed using thin film technology have been extensively investigated in the last two decades. Recently, considerable efforts have been made to develop systems for depositing polycrystalline, microcrystalline or amorphous semiconductor materials, each of which can encompass relatively large areas, and which can be doped to form p-type and n-type materials for the production of p-i-n and n-i-p type photovoltaic devices which are, in operation, substantially equivalent to their crystalline counterparts. It is to be noted that the term "amorphous", as used herein, includes all materials or alloys which have no long range order, although they may have short or intermediate range order or even contain, at times, crystalline inclusions.
It is now possible to prepare amorphous silicon alloys by glow discharge or vacuum deposition techniques, said alloys possessing (1) acceptable concentrations of localized defect states in the energy gaps thereof, and (2) high quality electrical and optical properties. Such deposition techniques are fully described in U.S. Pat. No. 4,226,898, entitled Amorphous Semiconductors Equivalent To Crystalline Semiconductors, issued in the names of Stanford R. Ovshinsky and Arun Madan on Oct. 7, 1980; U.S. Pat. No. 4,217,374, issued in the names of Stanford R. Ovshinsky and Masatsugu Izu on Aug. 12, 1980, also entitled Amorphous Semiconductors Equivalent To Crystalline Semiconductors; and U.S. Pat. No. 4,517,223, issued in the names of Stanford R. Ovshinsky, David D. Allred, Lee Walter, and Stephen J. Hudgens on May 14, 1985 and entitled Method Of Making Amorphous Semiconductor Alloys And Devices Using Microwave Energy. As disclosed in these patents, which are assigned to the assignee of the instant invention and the disclosure of which are incorporated by reference, fluorine introduced into the amorphous silicon semiconductor layers operates to substantially reduce the density of the localized defect states therein and facilitates the addition of other alloying materials, such as germanium.
To enhance photovoltaic device efficiency, multiple photovoltaic cells are used. When these cells are arranged in layers, the individual cells are often provided with different band gaps to more efficiently collect various portions of the spectrum of light incident upon the cells, and to increase open circuit voltage (Voc). A tandem cell device is by definition a device which has two or more cells with the light directed serially through each cell. In the first cell, a large band gap material may absorb only the shorter wavelength light while in subsequent cells smaller band gap materials may absorb the longer wavelengths of light which pass through the first cell. The overall open circuit voltage in such a tandem device is the sum of the open circuit voltage of each cell. Such multiple cells preferably include a back reflector for increasing the percentage of incident light reflected from the substrate back through the semiconductor layers of the cells.
Considerable efforts are also being made to fabricate transistors and other semiconductor devices useful in integrated electronic circuits of non-crystalline semiconductor materials, such as amorphous silicon alloys. Such transistors are normally formed of thin films of deposited conductive, insulating, and amorphous semiconductor materials, and therefore are often called thin film transistors, or TFTs. Such TFTs are normally transistors in which the gate is insulated from the conductive channel between its two current carrying electrodes, and in which a voltage must be applied to to the gate in order to shift the Fermi level in the conduction channel sufficiently, so as to make the normally non-conducting channel conducting. Examples of such TFTs and descriptions of how they may be made are found in U.S. Pat. No. 4,547,789 entitled High Current Thin Film Transistor which issued on Oct. 15, 1985, U.S. Pat. No. 4,543,320 entitled Method Of Making A High Performance, Small Area Thin Film Transistor which issued on Sept. 24, 1985, and U.S. patent application Ser. No. 549,996 entitled High Performance, Small Area Thin Film Transistor, filed in the names of H. Fritzsche and R. Johnson on Nov. 8, 1983, and U.S. patent application Ser. No. 723,103 entitled Thin Film Transistor, filed in the names of R. Flasck and S. Holmberg on June 3, 1985. These patents and applications are also assigned to the assignee of the present invention and are hereby incorporated by reference herein.
Several major advancements in thin film transistor technology have been very recently made, and are described in detail in U.S. patent application Ser. No. 788,594 entitled Double Injection Field Effect Transistors, filed in the names of W. Czubatyj, M. Hack and M. Shur on Oct. 17, 1985. This application is also assigned to the assignee of the present invention, and is hereby incorporated by reference herein. This application is also assigned to the assignee of the present invention, and is hereby incorporated by reference herein. Although most of all the new transistor devices described therein are illustrated as amorphous semiconductor devices, the new principles announced therein are largely applicable to crystalline, polycrystalline, and microcrystalline devices as well. The double injection devices described therein operate by modulating the density and/or cross section of ambipolar current (which may be described as a plasma of electrons and holes) by using an electric field that extends along the current path and typically projects perpendicularly in to the current path. The devices are preferably constructed as field effect transistors having ambipolar current in the body of semiconductor between the current-carrying electrodes, which are called the anode and cathode. Both junction field effect transistors and insulated gate field effect transistors are described therein. Vertically arranged and horizontally arranged double injection field effect transistors are shown therein. The vertical embodiments of such transistors are called vertical modulated injection transistors (VMITs), and are formed by successively depositing various layers of conductive and semiconductive materials. The conductive layers serving as the gate of the transistor may or may not be insulated. Certain of these transistors feature multiple gates whic.h can be configured as AND, NOR or other logic gates. Certain embodiments of the DIFET disclosed in U.S. patent application Ser. No. 788,594 use space charged neutralization for even higher current handling capabilities. Some DIFETs disclosed therein, made preferably of amorphous silicon alloys, exhibit light emission. A DIFET laser made from such alloys is disclosed therein. Modulation of the amplitude and/or frequency of the DIFETs optical output by varying the gate voltage is also disclosed. Two of the electro-optical versions of the DIFET disclosed in application Ser. No. 788,594 are described further below, since they are shown in a number of illustrative embodiments of the present invention. These DIFET devices should prove to be of value in and spur the development of thin film circuits, chips and memories, some of which will be briefly described.
Integrated electronic structures may be made from thin film devices. One class of examples are the programmable electronic matrix arrays shown in U.S. Pat. No. 4,545,111 entitled Method Of Making, Parallel Preprogramming Or Field Programming Of Electronic Matrix Arrays which issued on Oct. 8, 1985, and U.S. Pat. No. 4,499,557 entitled Programmable Cell For Use In Programmable Electronic Arrays which issued on Feb. 12, 1985.
Very recently, the interest in three dimensional integrated electronic circuit structures has grown. Such structures may contain a million or more cells or various electronic devices, such as diodes and bistate memory devices. Several such structures are disclosed, for example, in U.S. patent application No. 655,961 entitled Programmable Semiconductor Structures And Methods For Using The Same, filed in the names of S. R. Ovshinsky, et al. on Sept. 28, 1984. Among other things, this application discloses multilayered structures of deposited layers of various materials including semiconductor alloy materials which are initially deposited as continuous layers. One type of structure disclosed is a programmable logic array having a plurality of vertically arranged layers initially deposited as continuous layers, and subsequently patterned to provide semiconductor interactions to implement individually programmable selected logic functions in various locations. Another type of multilayer structure disclosed therein has two or more programmable logic planes, one of which may be an AND logic plane and another of which may be an OR logic plane. This application also teaches various methods for interconnecting the layers of such a multilayered structure using vertically arranged conductors, and techniques for interconnecting such a structure to external electronic circuits, such as by down bonding leads to terminal pads on the various layers.
Such three dimensional integrated circuit structure are preferably constructed by using multiple layers of various thin film materials including amorphous semiconductor alloy materials, metallic conductors and insulating materials. As the number or the density of device in such structures is increased, the issues of how to efficiently, economically and reliably make connections between devices located on different planes of the structure, and of how to best communicate with devices and circuits external to the structure become increasingly important. One aspect of such connections or communication paths which deserves consideration, particularly in high density three dimensional structures, is electrical noise or cross talk between devices and conductors on the same plane, or on different planes of the device, or on conductors connecting the integrated structure to external circuit devices. It would be very advantageous to have connections and communication paths which inherently have a low susceptibility to electrical noise or cross-talk to minimize any potential problems in this regard. It would be advantageous to have a technique for building three dimensional structures which inherently minimize the electrical noise or cross talk between layers.
One of the distinct advantages of thin film devices and thin film integrated electronic structures is that they may be fabricated in very large areas, thus making possible the implementation of very large scale integration (VLSI) and ultra-large scale integration (ULSI) electronic circuitry, without the use of costly one micron or submicron geometries. Larger and much less expensive feature sizes, such as 5 microns to 20 microns or more may be used, since thin films may be reliably deposited and patterned over very large areas, with greater ease and higher yields than their crystalline counterpart semiconductors may be. Also, unlike crystalline silicon which must be epitaxially grown upon a crystalline silicon substrate, making it very difficult to build multiple layers of circuitry, thin films may be deposited in multiple layers or planes of devices, thereby yielding truly three dimensional structures. Accordingly, the assignee of the present invention is working to develop ultra-large capacity three dimensional thin film amorphous semiconductor memories and the necessary technology to construct a fully integrated thin film central processing unit or computer made from amorphous semiconductor materials.
In VLSI and ULSI electronic structures, transmission delays can be experienced over long conductors due to the capacitance of the conductors and its associated connections to various device electrodes. Also, as the number of long conductors in such a structure increases, device layout and conductor routing problems becomes more complex. Thus, any technqiues or devices which could alleviate such delays or reduce the number of long conductors would be quite beneficial.
Also, there is a great interest in developing large area flat panel displays using amorphous semiconductor technology. Those in flat panel display field recognize that one important technique for reducing the costs of such large area displays would be to fabricate the driver, logic, and addressing circuitry required for the active matrix of the displays on the glass substrate at the same time the amorphous thin film logic and/or switching elements for each pixel for the flat panel matrix are formed. However, as the number of active devices on the glass substrate increases, so too does the need for high speed, reliable control signal paths and data paths, both on the display substrate and between the substrate and the external circuits which provides the video and control information necessary to drive the display.
Accordingly, there is an on-going desire to improve the speed, current carrying capacity, over-all performance, reliability, noise immunity and ease of fabrication of all such thin film devices, and of all communication paths in thin film integrated electronic structures.